8T49N282_16 Datasheet, PDF (60/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N282 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
CLKx/nCLKx Input
For applications not requiring the use of one or more reference clock
inputs, both CLKx and nCLKx can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
CLKx to ground. It is recommended that CLKx, nCLKx not be driven
with active signals when not enabled for use by either PLL.
LVCMOS Control Pins
All control pins have internal pullup or pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z_T) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z₀) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
Outputs:
LVPECL Outputs
Any unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
Any unused LVDS output pair can be either left floating or terminated
with 100 across. If they are left floating there should be no trace
attached.
LVCMOS Outputs
Any LVCMOS output can be left floating if unused. There should be
no trace attached.
standard termination schematic as shown in Figure 12A can be used
with either type of output structure. Figure 12B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS
Driver
Z_O  Z_T
Z_T
LVDS
Receiver
Figure 12A. Standard LVDS Termination
LVDS
Driver
Z_O  Z_T
Figure 12B. Optional LVDS Termination
©2016 Integrated Device Technology, Inc.
Z_T
2 _LVDS
C
Z_T ^Receiver
2
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Revision H, October 26, 2016