IDT72V70180 Datasheet, PDF (6/20 Pages) Integrated Device Technology – 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128 3.3V Power Supply

IDT72V70180 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 128 x 128
COMMERCIAL TEMPERATURE RANGE
CONNECTION MEMORY CONTROL
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 4 for detail.
The processor channel (PC) bit of the connection memory selects between
Processor Mode and Connection Mode. If high, the contents of the connection
memory are output on the TX streams. If low, the stream address bit (SAB) and
the channel address bit (CAB) of the connection memory defines the source
information (stream and channel) of the time-slot that will be switched to the output
from data memory.
The V/C (Variable/Constant Delay) bit in each connection memory location
allows the per-channel selection between variable and constant throughput
delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70180
After power up, the state of the connection memory is unknown. As such,
the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
Control Register ^CR_b^{7 CR}_b^{6 CR}_b^{5 CR}_b^{4 CR}_b^{3 CR}_b^{2 CR}_b^{1 CR}_b⁰
CR_b4
0
1
The Control Register is only accessed when A7-A0
are all zeroed. When A7 =1, up to 32 bytes are
randomly accessable via A0-A4 at any one instant.
Of which stream these bytes (channels) are accessed
is determined by the state of CRb1 -CRb0.
Connection Memory
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Data Memory
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
CR_b1
0
0
1
1
CR_b0 Stream
0
0
1
1
0
2
1
3
10000000 10000001
10000010
10011111
Figure 3. Addressing Internal Memories
6
External Address Bits A7-A0
5716 drw03