ICS97U870AKIT Datasheet, PDF (6/13 Pages) Integrated Device Technology – 1.8V Wide Range Frequency Clock Driver

ICS97U8 7 0
Advance Information
Timing Requirements
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
freq_op
1.8V+0.1V @ 25°C
95
370
Application Frequency
Range
freq_App
1.8V+0.1V @ 25°C
160
350
Input clock duty cycle
d_tin
40
60
UNITS
MHz
MHz
%
CLK stabilization
T_STAB
15
µs
Switching Characteristics¹
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN TYP
Output enable time
t_en
OE to any output
4.73
Output disable time
t_dis
OE to any output
5.82
Period jitter
t_{jit (per)}
-30
Half-period jitter
Input slew rate
t_jit(hper)
-60
Input Clock
1
2.5
SLr1(i)
Output Enable (OE), (OS) 0.5
Output clock slew rate
Cycle-to-cycle period jitter
SLr1(o)
t_jit(cc+)
t_jit(cc-)
1.5
2.5
0
0
Dynamic Phase Offset
Static Phase Offset
Output to Output Skew
SSC modulation frequency
t_{( )dyn}
t_SPO2
t_skew
-20
-50
0
30.00
SSC clock input frequency
0.00
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
MAX
8
8
30
60
4
3
40
-40
20
50
40
33
UNITS
ns
ns
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
kHz
-0.50 %
MHz
0817—07/07/03
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