ICS830154AMI-08LF Datasheet, PDF (6/16 Pages) Integrated Device Technology – Over-Voltage Tolerant 1.5V, 1:4 Fanout Buffer

ICS830154I-08 Data Sheet
OVER-VOLTAGE TOLERANT 1.5V, 1:4 FANOUT BUFFER
Table 5B. AC Characteristics, V_DD = 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
f_OUT
tp_LH
Output Frequency
Propagation Delay
(low to high transition); NOTE 1
tp_HL
Propagation Delay
(high to low transition); NOTE 1
t_PLZ, t_PHZ
Disable Time
(active to high-impedance)
t_PZL, t_PZH
Enable Time
(high-impedance to disable)
tsk(o)
Output Skew; NOTE 2, 3
tsk(pp) Part-to-Part Skew; NOTE 2, 4
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
Minimum
0.8
0.8
0.35
48
Typical
0.076
Maximum
160
1.7
Units
MHz
ns
1.7
ns
10
ns
10
ns
250
ps
800
ps
ps
1.2
ns
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to F_OUT ≤ 150MHz.
NOTE 1: Measured from the V_DD/2 of the input to V_DD/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DD/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DD/2.
Table 5C. AC Characteristics, V_DD = 1.8V ± 0.15V, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
f_OUT
tp_LH
Output Frequency
Propagation Delay
(low to high transition); NOTE 1
tp_HL
Propagation Delay
(high to low transition); NOTE 1
t_PLZ, t_PHZ
Disable Time
(active to high-impedance)
t_PZL, t_PZH
Enable Time
(high-impedance to disable)
tsk(o)
Output Skew; NOTE 2, 3
tsk(pp) Part-to-Part Skew; NOTE 2, 4
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
0.63V to 1.17V
For NOTES, see Table 5B above.
Minimum
1.1
1.1
0.12
47
Typical
0.193
Maximum
160
2.1
Units
MHz
ns
2.1
ns
10
ns
10
ns
250
ps
800
ps
ps
0.6
ns
53
%
ICS830154AGI-08 REVISION A MARCH 29, 2010
6
©2010 Integrated Device Technology, Inc.