ICS581-01 Datasheet, PDF (6/10 Pages) Integrated Circuit Systems – Zero-Delay Glitch-Free Clock Multiplexer

ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
Parameter
Input Capacitance
Output High Voltage
Output Low Voltage
Short Circuit Current
On-chip Pull-up
Resistor
Symbol Conditions
C_IN
V_OH
V_OL
I_OS
R_PU
I_OH = -12 mA
I_OL = 12 mA
Min.
VDD-0.5
S1=0, OE1=0,
SELA, DIV pins
Typ.
5
±70
250
Max.
0.5
Units
pF
V
V
mA
k
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 C
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
f_IN
6
Input Clock Duty Cycle
at VDD/2
30
Skew
t_SKEW
selected input clock to
FBIN, Note 1
between any output
clocks, Note 2
-250 0
-250 0
Max.
200
70
250
250
Transition Detector
Timeout
ICS581-02 only
DIV = 0
DIV = 1
2
3
4
32
48
64
Frequency Transition Time
t_TRAN
50 to 150 MHz, Note 3, 4
100 to 100 MHz, Note 3,
5
70 200
4
10
Output Clock Rise Time
Output Clock Fall Time
t_OR 0.8 V to 2.0 V
t_OF 2.0 V to 0.8 V
less than 133 MHz
at VDD/2, no load
1
2
1
2
45
55
Output Clock Duty Cycle
greater than 133 MHz
at VDD/2, no load
40
60
with S0=S1=1
at VDD/2, no load
40
60
Absolute Output Clock
Period Jitter
t_JA Deviation from mean
±150
One Sigma Output Clock
Period Jitter
t_JA
40
Units
MHz
%
ps
ps
INB
periods
INB
periods
s
s
ns
ns
%
%
%
ps
ps
Note 1: Assumes clocks with same rise times, measured at VDD/2.
Note 2: Assumes identically loaded outputs with identical rise times, measured at VDD/2. The maximum skew between any two
clocks is 250 ps not 500 ps.
Note 3: Time taken for output to lock to new clock when mux selection changed from INA to INB.
Note 4. With 50 MHz on INA and 150 MHz on INB.
Note 5: With 100 MHz on both INA and INB, 180 out of phase.
IDT® ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
6
ICS581-01/02 REV M 110216