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ICS345 Datasheet, PDF (6/9 Pages) Integrated Circuit Systems – Triple PLL Field Programmable SS VersaClock Synthesizer
ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Input Frequency
FIN Fundamental crystal
5
Input clock
2
Output Frequency
VDD=3.3 V
0.25
Output Rise Time
Output Fall Time
Duty Cycle
tOR 20% to 80%, Note 1
tOF 80% to 20%, Note 1
Note 2
40
Output Frequency Synthesis
Error (Note 4)
Configuration Dependent
Power-up Time
PLL lock-time from
power-up, Note 3
PDTS goes high until stable
CLK output, Spread
Spectrum Off, Note 3
PDTS goes high until stable
CLK output, Spread
Spectrum On, Note 3
One Sigma Clock Period Jitter
Configuration Dependent
Maximum Absolute Jitter
tja
Deviation from Mean.
Configuration Dependent
Pin-to-Pin Skew
Low Skew Outputs
-250
Typ.
1
1
49-51
0
4
0.2
4
50
+200
Max. Units
27 MHz
50 MHz
200 MHz
ns
ns
60
%
ppm
10 ms
2
ms
7
ms
ps
ps
250 ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Note 3: IDT test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS transition
high on select address change.
Note 4: The actual ppm error will be displayed in the VersaClock software when the programming file is generated
for the customer’s specific configuration. In general, zero ppm error can be achieved, but please note that the
device cannot improve upon the error of the input reference clock. For example, if the input crystal has 25 ppm error,
then the outputs will also have 25 ppm error.
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
Thermal Resistance Junction to Case θJC
Min.
Typ.
135
93
78
60
Max. Units
° C/W
° C/W
° C/W
° C/W
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6
ICS345
REV K 110207