DAC1401D125HL-C1 Datasheet, PDF(6/25 Page) Integrated Device Technology

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DAC1401D125HL-C1 Datasheet, PDF (6/25 Pages) Integrated Device Technology – Dual 14-bit DAC, up to 125 Msps

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Integrated Device Technology

DAC1401D125

Dual 14-bit DAC, up to 125 Msps

Table 5. Characteristics â¦continued

VDDD = VDDA = 3.3 V; AGND and DGND connected together; IO(fs) = 20 mA and Tamb = ï40 ï°C to +85 ï°C; typical values

measured at Tamb = 25 ï°C.

Symbol Parameter

Conditions

Min

Typ Max

Unit

Digital inputs

VIL

LOW-level input voltage

VIH

HIGH-level input voltage

IIL

LOW-level input current VIL = 0.9 V

IIH

HIGH-level input current VIH = 1.3 V

input capacitance

Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)

DGND

0.9

1.3

VDDD

ïA

[1] -

IO(fs)

full-scale output current differential outputs

output voltage

compliance range

output resistance

output capacitance

Reference voltage input/output (REFIO)

[1] ï1

[1] -

+1.25

150 -

kï

VO(ref)

reference output voltage

IO(ref)

reference output current

input voltage

input resistance

Input timing see Figure 18

compliance range

1.21

1.26 1.31

[1] -

100 -

1.0

1.26

Mï

sampling frequency

tw(WRT)

WRT pulse width

pins WRTA, WRTB

tw(CLK)

CLK pulse width

pins CLKA, CLKB

th(i)

input hold time

tsu(i)

input set-up time

Output timing (IOUTAP, IOUTAN, IOUTBP, IOUTBN)

125

1.8

Msps

delay time

transition time

rising or falling transition

[1] -

0.6

(10 % to 90 % or 90 % to 10 %)

settling time

Static linearity

ï±1 LSB

[1] -

INL

integral non-linearity

25 ï°C

ï±1.60

ï±2.15 ï±2.90

LSB

ï40 ï°C to +85 ï°C

ï±1.25

ï±2.95

LSB

DNL

differential non-linearity ï40 ï°C to +85 ï°C

ï±0.55

ï±0.75 ï±1.10

LSB

Static accuracy (relative to full-scale) with GAINCTRL = 0

Eoffset

offset error

gain error

with external reference

with internal reference

-0.02

+0.02

-1.9

ï±1.5 +2.5

-2.9

ï±2.1 +2.9

ïG

gain mismatch

between DAC A and DAC B

-0.5

ï±0.05 +0.5

DAC1401D125 3

Product data sheet

Rev. 03 â 2 July 2012

6 of 25

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