9FGV0631C Datasheet, PDF (6/15 Pages) Integrated Device Technology – Outputs can optionally be supplied from any voltage

9FGV0631C DATASHEET
Electrical Characteristics–Input/Supply/Common Output Parameters–Normal
Operating Conditions
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDxx ^{Supply voltage for core, analog and single-ended}
1.7
1.8
1.9
V
LVCMOS outputs
Output Supply Voltage
VDDIO Supply voltage for differential Low Power Outputs 0.9975 1.05-1.8 1.9
V
Ambient Operating
Temperature
T_AMB
Commmercial range
Industrial range
0
25
70
°C
-40
25
85
°C
Input High Voltage
V_IH
Single-ended inputs, except SMBus
0.75 V_DD
V_DD + 0.3 V
Input Mid Voltage
V_IM
Single-ended tri-level inputs ('_tri' suffix)
0.4 V_DD 0.5 V_DD 0.6 V_DD
V
Input Low Voltage
V_IL
Single-ended inputs, except SMBus
-0.3
0.25 V_DD V
Output High Voltage
V_IH
Single-ended outputs, except SMBus. I_OH = -2mA V_DD-0.45
V
Output Low Voltage
V_IL
Single-ended outputs, except SMBus. I_OL = -2mA
0.45
V
Input Current
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
5
uA
200
uA
V_IN = VDD; Inputs with internal pull-down resistors
Input Frequency
F_in
XTAL, or X1 input
23
25
27
MHz
Pin Inductance
L_pin
7
nH
1
Capacitance
C_IN
Logic Inputs, except DIF_IN
1.5
C_OUT
Output pin capacitance
5
pF
1
6
pF
1
Clk Stabilization
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.6
1.8
ms
1,2
SS Modulation Frequency
f_MOD
Allowable Frequency
(Triangular Modulation)
30
31.6
33
kHz
1
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
3
3
clocks 1,3
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
20
300
us
1,3
Tfall
t_F
Fall time of single-ended control inputs
5
ns
2
Trise
t_R
Rise time of single-ended control inputs
5
ns
2
SMBus Input Low Voltage V_ILSMB
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
0.6
V
SMBus Input High Voltage V_IHSMB
V_DDSMB = 3.3V, see note 5 for V_DDSMB < 3.3V
2.1
3.6
V
4
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
0.4
V
SMBus Sink Current
I_PULLUP
@ V_OL
4
mA
Nominal Bus Voltage
V_DDSMB
1.7
3.6
V
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_FSMB
f_MAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
300
ns
1
400
kHz
1
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Control input must be monotonic from 20% to 80% of input swing.}
3 _{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VIHSMB >= 0.65xVDDSMB}
6-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR
6
REVISION A 09/30/14