9FGV0231_17 Datasheet, PDF (6/16 Pages) Integrated Device Technology – 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

9FGV0231
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1.8V Supply Voltage
VDD
Supply voltage for core, analog and single-ended
LVCMOS outputs
Ambient Operating
T_COM
Commercial range
Temperature
T_IND
Industrial range
Input High Voltage
V_IH
Single-ended inputs, except SMBus
Input Mid Voltage
V_IM Single-ended tri-level inputs ('_tri' suffix, if present)
Input Low Voltage
V_IL
Schmitt Trigger Positive
Going Threshold Voltage
V_T+
Single-ended inputs, except SMBus
Single-ended inputs, where indicated
Schmitt Trigger Negative
Going Threshold Voltage
V_T-
Single-ended inputs, where indicated
Hysteresis Voltage
V_H
V_T+ - V_T-
Output High Voltage
V_IH
Single-ended outputs, except SMBus. I_OH = -2mA
Output Low Voltage
V_IL
Single-ended outputs, except SMBus. I_OL = -2mA
Input Current
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
V_IN = VDD; Inputs with internal pull-down resistors
Input Frequency
F_in
XTAL, or X1 input
Pin Inductance
L_pin
Capacitance
C_IN
C_OUT
Logic Inputs, except DIF_IN
Output pin capacitance
Clk Stabilization
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
SS Modulation Frequency
f_MOD
Allowable Frequency
(Triangular Modulation)
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
t_F
Fall time of single-ended control inputs
Trise
t_R
Rise time of single-ended control inputs
SMBus Input Low Voltage V_ILSMB
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
SMBus Input High Voltage V_IHSMB
V_DDSMB = 3.3V, see note 5 for V_DDSMB < 3.3V
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
SMBus Sink Current
I_PULLUP
@ V_OL
Nominal Bus Voltage
V_DDSMB
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_FSMB
f_MAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Control input must be monotonic from 20% to 80% of input swing.}
3 _{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB}
5 _{For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB}
1.7
0
-40
0.75 V_DD
0.4 V_DD
-0.3
0.4 V_DD
0.1 V_DD
0.1 V_DD
V_DD-0.45
-5
-200
23
1.5
31
1
2.1
4
1.7
1.8
25
25
25
0.6
31.6
2
1.9
V
70
°C
85
°C
V_DD + 0.3 V
0.6 V_DD
V
0.25 V_DD V
0.7 V_DD
V
0.4 V_DD
V
0.4 V_DD
V
V
0.45
V
5
uA
200
uA
27
MHz
7
nH
5
pF
6
pF
1.8
ms
32
kHz
3
clocks
300
us
5
ns
5
ns
0.8
V
3.6
V
0.4
V
mA
3.6
V
1000
ns
300
ns
400
kHz
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
6
9FGV0231
JUNE 22, 2017