9DBU0731 Datasheet, PDF (6/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0731 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
1.425
1.5
1.575
V
Output Supply Voltage
VDDIO
Low Voltage Supply LP-HCSL Outputs
0.95 1.05-1.5 1.575
V
Ambient Operating
Temperature
T_AMB
Commercial range
Industrial range
0
25
70
°C
1
-40
25
85
°C
1
Input High Voltage
V_IH
Single-ended inputs, except SMBus
0.75 V_DD
V_DD + 0.3 V
Input Mid Voltage
V_IM
Single-ended tri-level inputs ('_tri' suffix)
0.4 V_DD
0.6 V_DD
V
Input Low Voltage
V_IL
Single-ended inputs, except SMBus
-0.3
0.25 V_DD V
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
5
µA
Input Current
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
V_IN = VDD; Inputs with internal pull-down resistors
200
µA
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
F_in
L_pin
C_IN
C_{INDIF_IN}
C_OUT
T_STAB
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
f_MODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency non-PCIe
f_MODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_F
t_R
V_ILSMB
V_IHSMB
V_OLSMB
I_PULLUP
V_DDSMB
t_RSMB
t_FSMB
f_MAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
@ I_PULLUP
@ V_OL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4 _{For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB}
5_{DIF_IN input}
6_{The differential input clock must be running for the SMBus to be active}
1
1.5
1.5
30
0
1
2.1
4
1.425
167
MHz
2
7
nH
1
5
pF
1
2.7
pF
1,5
6
pF
1
1
ms
1,2
33
kHz
66
kHz
3
clocks 1,3
300
µs
1,3
5
ns
2
5
ns
2
0.6
V
3.3
V
4
0.4
V
mA
3.3
V
1000
ns
1
300
ns
1
400
kHz
6
7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER
6
MARCH 8, 2017