9DBU0541_17 Datasheet, PDF (6/17 Pages) Integrated Device Technology – 5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms

9DBU0541 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_AMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
Ambient Operating
Temperature
T_AMB
Commercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
V_IH
V_IM
V_IL
I_IN
I_INP
F_in
L_pin
C_IN
C_{INDIF_IN}
C_OUT
T_STAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, V_IN = GND, V_IN = VDD
Single-ended inputs
V_IN = 0 V; inputs with internal pull-up resistors
V_IN = VDD; inputs with internal pull-down resistors
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From V_DD power-up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
f_MODINPCIe
Allowable frequency for PCIe applications
(Triangular modulation)
Input SS Modulation
Frequency non-PCIe
f_MODIN
Allowable frequency for non-PCIe applications
(Triangular modulation)
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_F
t_R
V_ILSMB
V_IHSMB
V_OLSMB
I_PULLUP
V_DDSMB
t_RSMB
t_FSMB
f_MAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
at I_PULLUP
at V_OL
Bus voltage
(Max VIL - 0.15V) to (Min VIH + 0.15V)
(Min VIH + 0.15V) to (Max VIL - 0.15V)
Maximum SMBus operating frequency
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Control input must be monotonic from 20% to 80% of input swing.}
3 _{Time from deassertion until outputs are > 200 mV.}
4 _{For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB}
5 _{DIF_IN input.}
6 _{The differential input clock must be running for the SMBus to be active.}
1.425
0
-40
0.75 V_DD
0.4 V_DD
-0.3
-5
-200
1
1.5
1.5
30
0
1
2.1
4
1.425
1.5
1.575
V
25
70
°C
1
25
85
°C
1
V_DD + 0.3 V
0.6 V_DD
V
0.25 V_DD V
5
µA
200
µA
167
MHz
2
7
nH
1
5
pF
1
2.7
pF
1,5
6
pF
1
1
ms
1,2
33
kHz
66
kHz
3
clocks 1,3
300
µs
1,3
5
ns
2
5
ns
2
0.6
V
3.3
V
4
0.4
V
mA
3.3
V
1000
ns
1
300
ns
1
400
kHz
6
5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS
6
MARCH 9, 2017