89HP0504PB Datasheet, PDF (6/26 Pages) Integrated Device Technology – 4 Channel 5Gbps PCIe® Signal Repeater

IDT 89HP0504PB Data Sheet
Power-Up
After the power supplies reach their minimum required levels, the P0504PB powers up by setting all input and output pins to known states:
‹ _{All the device's input configuration pins are set internally to VSS or VDD for 2-level pins and to VDD/2 for 3-level pins.}
‹ _{High speed differential input and output pins depend on various conditions described below:}
– High speed differential input and output pins are in high impedance if any of the following conditions is true:
• Powerdown is set (PDB pin = 0V) or
• No receiver termination was detected at TX outputs
In all other cases, high speed differential input and output pins are set to 50 ohms per pin, with 100 ohms differential impedance. Also refer to
Table 4, Power Reducing Modes, Table 2, Receiver Impedance, and Table 3, Transmitter Impedance.
The power ramp up time for the P0504PB should be less than 1ms.
Power Sequencing
There are no power sequencing constraints for the P0504PB.
IDT EyeBoost™ Technology
IDT EyeBoost™ technology is a method of data stream recovery even when the differential signal eye is completely closed due to cable or trace
attenuation and ISI jitter. With IDT EyeBoost™, the system designer can both recover the incoming data and retransmit it to target device with a
maximized eye width and amplitude. An example of IDT EyeBoost™ technology usage in a system application and eye diagram results are shown in
Figure 4. In this figure, the (a) diagram shows incoming differential signal (closed eye) after 62 inch FR4 connection from signal source and the (b)
diagram shows differential signal at the output of repeater maximized eye opening with IDT EyeBoost™ technology.
(a)
(b)
Figure 4 Eye Diagram
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February 8, 2011