7028L20PFI Datasheet, PDF (6/7 Pages) Integrated Device Technology – FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET

IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
TEST CIRCUITS AND WAVEFORMS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
V CC
VIN
Pulse
Generator
D.U.T
.
R^T
VOUT
500Ω
50pF
500Ω
CL
Octal link
Test Circuits for All Outputs
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
DATA
INPUT
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
ETC.
tH
tREM
tH
Set-Up, Hold, and Release Times
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
Octal link
LOW-HIGH-LOW
PULSE
tW
HIGH-LOW-HIGH
PULSE
Pulse Width
1.5V
1.5V
Octal link
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Propagation Delay
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
Octal link
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
3V
1.5V
tPZL
0V
tPLZ
SWITCH
CLOSED
tPZH
3.5V
1.5V
tPHZ
3.5V
0.3V _VOL
SWITCH
OPEN
1.5V
0V
0.3V ^VOH
0V
Octal link
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6