IDT82V3288 Datasheet, PDF (59/170 Pages) Integrated Device Technology – WAN PLL

IDT82V3288
CS
tsu2
tpw2
th2
SCLK
SDI
th1
tsu1
tpw1
R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
High-Z
SDO
Figure 25. Serial Write Timing Diagram
Table 41: Write Timing Characteristics in Serial Mode
Symbol
Parameter
Min
Typ
Max
T
One cycle time of the master clock
t_in
Delay of input pad
t_out
Delay of output pad
t_su1
Valid SDI to valid SCLK setup time
4
t_su2
Valid CS to valid SCLK setup time
14
t_pw1
SCLK pulse width low
3.5T
t_pw2
SCLK pulse width high
3.5T
t_h1
Valid SDI after valid SCLK hold time
6
t_h2
Valid CS after valid SCLK hold time
5
t_TI
Time between consecutive Write-Write or Write-Read accesses
(CS rising edge to CS falling edge)
10
12.86
5
5
WAN PLL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface
59
June 22, 2006