92HD99B Datasheet, PDF (59/225 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD99
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
Field Name
Rsvd3
StepSize
Rsvd2
NumSteps
Rsvd1
Offset
Bits
R/W
Default
Reset
30:23
R
00h
N/A (Hard-coded)
Reserved.
22:16
R
02h
N/A (Hard-coded)
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
R
0h
N/A (Hard-coded)
Reserved.
14:8
R
7Fh
N/A (Hard-coded)
Number of gains steps (number of possible settings - 1).
7
R
0h
N/A (Hard-coded)
Reserved.
6:0
R
7Fh
N/A (Hard-coded)
Indicates which step is 0dB
7.4.9. AFG (NID = 01h): PwrState
Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8)
Set
Get
F0500h
Byte 1 (Bits 7:0)
705h
Field Name
Rsvd3
SettingsReset
ClkStopOK
Error
Bits
R/W
Default
Reset
31:11
R
000000h
N/A (Hard-coded)
Reserved.
10
R
1h
POR - DAFG - ULR
Indicates if any persistent settings in this Function Group have been reset.
Cleared by PwrState 'Get' to this Widget.
9
R
1h
POR - DAFG - ULR
Bit clock can currently be removed: 1 = yes, 0 = no.
8
R
0h
POR - DAFG - ULR
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
IDT CONFIDENTIAL
59
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
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92HD99