IDT82V3358 Datasheet, PDF (58/139 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL

IDT82V3358
SYNCHRONOUS ETHERNET WAN PLL
DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Address: 0AH
Type: Read / Write
Default Value: XXXXX00X
7
6
5
4
3
2
1
0
-
-
-
-
-
OSC_EDGE OUT1_PECL_LVDS
-
Bit
Name
Description
7-3
-
Reserved.
This bit selects a better active edge of the master clock.
2
OSC_EDGE 0: The rising edge. (default)
1: The falling edge.
This bit selects a port technology for OUT1.
1
OUT1_PECL_LVDS 0: LVDS. (default)
1: PECL.
0
-
Reserved
Programming Information
58
May 19, 2009