IDT82V3255 Datasheet, PDF (58/127 Pages) Integrated Device Technology – WAN PLL

IDT82V3255
WAN PLL
6.2.2 INTERRUPT REGISTERS
INTERRUPT_CNFG - Interrupt Configuration
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
7
6
5
4
3
2
1
0
-
-
-
-
-
-
HZ_EN
INT_POL
Bit
Name
Description
7-2
-
Reserved.
This bit determines the output characteristics of the INT_REQ pin.
1
HZ_EN
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt
is inactive. (default)
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0
INT_POL 0: Active low. (default)
1: Active high.
INTERRUPTS1_STS - Interrupt Status 1
Address: 0DH
Type: Read / Write
Default Value: XX1111XX
7
6
5
4
3
2
1
0
-
-
IN2_DIFF
IN1_DIFF
IN2_CMOS
IN1_CMOS
-
-
Bit
Name
Description
7-6
-
Reserved.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_DIFF; i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_DIFF bit (b5/4, 4AH). Here n is 2 or 1.
5-4
INn_DIFF 0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_CMOS; i.e.,
whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_CMOS bit (b3/2, 4AH). Here n is 2 or 1.
3-2
INn_CMOS 0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
1-0
-
Reserved.
Programming Information
58
June 19, 2006