IDT82V3280_08 Datasheet, PDF (56/171 Pages) Integrated Device Technology – WAN PLL

IDT82V3280
WAN PLL
5.5 SERIAL MODE
In a read operation, the active edge of SCLK is selected by CLKE.
When CLKE is asserted low, data on SDO will be clocked out on the ris-
ing edge of SCLK. When CLKE is asserted high, data on SDO will be
clocked out on the falling edge of SCLK.
In a write operation, data on SDI will be clocked in on the rising edge
of SCLK.
CS
SCLK
SDI
SDO
tsu2
tpw2
th2
th1
tsu1
tpw1
R/W A0 A1 A2 A3 A4 A5 A6
High-Z
td1
t_d2
D0 D1 D2 D3 D4 D5 D6 D7
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low)
CS
th2
SCLK
SDI
SDO
R/W A0 A1 A2 A3 A4 A5 A6
High-Z
td1
td2
D0 D1 D2 D3 D4 D5 D6 D7
Figure 24. Serial Read Timing Diagram (CLKE Asserted High)
Table 39: Read Timing Characteristics in Serial Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
t_in
Delay of input pad
5
ns
t_out
Delay of output pad
5
ns
t_su1
Valid SDI to valid SCLK setup time
4
ns
t_su2
Valid CS to valid SCLK setup time
14
ns
t_d1
Valid SCLK to valid data delay time
t_d2
CS rising edge to SDO high impedance delay time
10
ns
10
ns
t_pw1
SCLK pulse width low
3.5T + 5
ns
t_pw2
SCLK pulse width high
3.5T + 5
ns
t_h1
Valid SDI after valid SCLK hold time
6
ns
t_h2
Valid CS after valid SCLK hold time (CLKE = 0/1)
5
ns
t_TI
Time between consecutive Read-Read or Read-Write accesses
(CS rising edge to CS falling edge)
10
ns
Microprocessor Interface
56
December 9, 2008