IDT82V1068 Datasheet, PDF (53/56 Pages) Integrated Device Technology – OCTAL PROGRAMMABLE PCM CODEC

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
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APPENDIX: IDT82V1068 COE-RAM MAPPING
INDUSTRIAL TEMPERATURE RANGE
Word#
39
32
31
24
23
16
15
8
7
0
b[2:0] Of a Coe-RAM
Command
100
011
010
001
000
channel8
channel7 Km RAM
channel6 Km RAM
channel5 Km RAM
channel4 Km RAM ACT RAM
channel3 Km RAM ACT RAM
channel2 Km RAM ACT RAM
channel1 Km RAM ACT RAM ACR RAM
GRX RAM
FRR RAM
ACT RAM
ACR RAM
ACT RAM ACR RAM
ACT RAM ACR RAM GTX RAM
GTX RAM
FRX RAM
ACR RAM
GTX RAM
ACR RAM GTX RAM
ACR RAM GTX RAM GRX RAM
GIS RAM GTX RAM ^{GRX RAM}
GTX RAM ^{GRX RAM}
FRR RAM GRX RAM
ECF RAM GRX RAM
GRX RAM
GRX RAM
IMF RAM
Figure 18 Coe-RAM Address Mapping
Generally, 6 bits of address are needed to locate each word of the 40 Coe-RAM words. The 40 words of Coe-RAM are divided into 5 blocks with 8
words per block in the IDT82V1068. So, only 3 bits of address are needed to locate each of the block. When the address of a Coe-RAM block (b[2:0])
is specified in a Coe-RAM Command, all 8 words of this block will be addressed automatically, with the highest order word first (The IDT82V1068 will
count down from '111' to '000' so that it accesses the 8 words successively). Refer to “3.1.8 Addressing the Coe-RAM” on page 26 for more
information.
The address assignment for the 40 words Coe-RAM is shown in Table 11. The number in the “Address” column is the actual hexadecimal address
of the Coe-RAM word. As the IDT82V1068 handles the lower 3 bits automatically, only the higher 3 bits (in bold style) are needed for a Coe-RAM
Command. It should be noted that, when addressing the GRX RAM, the FRR RAM will be addressed at the same time.
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