72T72115L5BBGI Datasheet, PDF (51/53 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 36 demonstrates a width expansion using two IDT72T7285/
72T7295/72T72105/72T72115 devices. D0 - D71 from each device form a
144-bit wide input bus and Q0-Q71 from each device form a 144-bit wide output
bus. Any word width can be attained by adding additional IDT72T7285/
72T7295/72T72105/72T72115 devices.
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
DATA IN
m+n
D0 - Dm ^m
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #1
FULL FLAG/INPUT READY (FF/IR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
Dm+1 - Dn
n
IDT
72T7285
72T7295
72T72105
72T72115
FIFO
#1
m
IDT
72T7285
72T7295
72T72105
72T72115
FIFO
#2
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
n _{Qm+1 - Qn}
m+n
DATA OUT
(1)
GATE
Q0 - Qm
5994 drw41
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of 16,384 x 144, 32,768 x 144, 65,536 x 144 and 131,072 x 144 Width Expansion
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