IDT72V15160 Datasheet, PDF (5/26 Pages) Integrated Device Technology – 3.3V MULTIMEDIA FIFO 16 BIT V-III, 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY

IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–Dn DataInputs
I Data inputs for a 16 or 32-bit bus
EF
Empty Flag
O EF indicates the FIFO memory is empty. See Table 2.
FF
Full Flag
O FF indicates the FIFO memory is full. See Table 2.
FSEL0⁽¹⁾ Flag Select Bit 0
I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
FSEL1⁽¹⁾ Flag Select Bit 1
I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
HF
Half-Full Flag
O HF indicates the FIFO memory is more than half-full. HF is asserted when the number of words written into the FIFO
reaches N÷2+1, where N is the total depth of the FIFO. See Table 2.
LD
Load
I During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines one of eight default offset
values for the PAE and PAF flags and serial programming mode. After Master Reset, LD must be high and should
only toggle LOW together with SEN to start serial loading of the flag offsets.
MRS MasterReset
I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for one of eight programmable flag default settings, serial programming of the offset settings and
synchronous versus asynchronous programmable flag timing modes.
OE
Output Enable
I OE controls the output line drivers.
PAE
Programmable
O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-Empty Flag
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
Programmable
O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-Full Flag
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PFM⁽¹⁾
PRS
Programmable
Flag Mode
Partial Reset
Q0–Qn
RCLK
REN
SEN
Data Outputs
Read Clock
Read Enable
Serial Enable
I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
will select Synchronous Programmable flag timing mode.
I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the serial programming method or programmable flag settings are all retained.
O Data outputs for an 16 or 32-bit bus. Outputs are not 5V tolerant regardless of the state of OE.
I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory.
I REN enables RCLK for reading data from the FIFO memory.
I SEN enables serial loading of programmable flag offsets. SEN must be high during Master Reset and should only
toggle LOW together with LD to start serial loading of the flag offsets.
SI
WCLK
WEN
Serial In
Write Clock
Write Enable
I At Maser Reset this pin is LOW. After Master Reset, this pin functions as a serial input for loading offset registers.
I Enabled by WEN, the rising edge of WCLK writes data into the FIFO.
I WEN enables WCLK for writing data into the FIFO memory.
VCC
+3.3V Supply
I These are VCC supply inputs and must be connected to the 3.3V supply rail.
GND Ground
I Ground Pins.
NOTE:
1. Inputs should not change state after Master Reset.
**Please continue to next page for more Pin descriptions for PBGA package.
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