IDT61298SA Datasheet, PDF (5/7 Pages) Integrated Device Technology – CMOS STATIC RAM 256K (64K x 4-BIT)

IDT61298SA
CMOS STATIC RAM 256K (64K x 4-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1⁽¹⁾
t RC
ADDRESS
OE
CS
DATAOUT
t AA
t OE
t OLZ ⁽⁵⁾
t ACS
t CLZ ⁽⁵⁾
TIMING WAVEFORM OF READ CYCLE NO. 2^(1,2,4)
tRC
ADDRESS
DATAOUT
tAA
tOH
TIMING WAVEFORM OF READ CYCLE NO. 3^(1,3,4)
CS
DATAOUT
VCC _ICC
SUPPLY
CURRENT _ISB
t ACS
t CLZ ⁽⁵⁾
t PU
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
7.1
COMMERCIAL TEMPERATURE RANGE
t OH
t OHZ ⁽⁵⁾
t CHZ ⁽⁵⁾
DATA VALID
2971 drw 05
tOH
DATA VALID
2971 drw 06
DATA VALID
t CHZ ⁽⁵⁾
t PD
2971 drw 07
5