IDT23S09E_09 Datasheet, PDF (5/8 Pages) Integrated Device Technology – 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (23S09E-1) - INDUSTRIAL^(1,2)
Symbol
Parameter
Conditions
Min.
t1 Output Frequency
10pF Load
10
30pF Load
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
t3 Rise Time
Measured between 0.8V and 2V
—
t4 Fall Time
Measured between 0.8V and 2V
—
t5 Output to Output Skew
All outputs equally loaded
—
t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
—
t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT23S09E only) 1
t7 Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
tJ Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Typ. Max. Unit
— 200 MHz
— 100
50
60 %
— 2.5 ns
— 2.5 ns
— 250 ps
0 ±350 ps
5
8.7 ns
0
700 ps
— 200 ps
—
1 ms
SWITCHING CHARACTERISTICS (23S09E-1H) - INDUSTRIAL^(1,2)
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
t1 Output Frequency
Duty Cycle = t2 ÷ t1
10pF Load
30pF Load
Measured at 1.4V, FOUT = 66.66MHz
10
— 200 MHz
10
— 100
40
50
60 %
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45
50
55 %
t3 Rise Time
Measured between 0.8V and 2V
—
—
1.5 ns
t4 Fall Time
Measured between 0.8V and 2V
—
—
1.5 ns
t5 Output to Output Skew
All outputs equally loaded
—
— 250 ps
t6A Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
—
t6B Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT23S09E only) 1
0 ±350 ps
5
8.7 ns
t7 Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700 ps
t8 Output Slew Rate
Measured between 0.8V and 2V using Test Circuit 2
1
—
— V/ns
tJ Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
— 200 ps
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1 ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
5