ICS9UMS9633B Datasheet, PDF (5/22 Pages) Integrated Device Technology – ULTRA MOBILE PC/MOBILE INTERNET DEVICE

ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
MLF Pin Description
PIN #
PIN NAME
1 CPU_STOP#
2 CLKPWRGD#/PD_3.3
3 X2
4 X1
5 VDDREF_3.3
6 REF
7 GNDREF
8 VDDCORE_3.3
9 FSC_L
10 TEST_MODE
11 TEST_SEL
12 SCLK_3.3
13 SDATA_3.3
14 VDDCORE_3.3
15 VDDIO_1.5
16 DOT96C_LPR
17 DOT96T_LPR
18 GNDDOT
19 GNDLCD
20 LCD100C_LPR
21 LCD100T_LPR
22 VDDIO_1.5
23 VDDCORE_3.3
24 *CR#0
TYPE
DESCRIPTION
IN Stops all CPU clocks, except those set to be free running clocks
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
IN are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
OUT
IN
PWR
OUT
PWR
PWR
IN
IN
IN
IN
I/O
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
IN
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Power pin for the XTAL and REF clocks, nominal 3.3V
14.318 MHz reference clock.
Ground pin for the REF outputs.
3.3V power for the PLL core
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V power for the PLL core
Power supply for low power differential outputs, nominal 1.5V.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
Ground pin for DOT clock output
Ground pin for LCD clock output
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
Power supply for low power differential outputs, nominal 1.5V.
3.3V power for the PLL core
Clock request for SRC0, 0 = enable, 1 = disable
IDT^TM/ICS^TM Ultra Mobile PC/Mobile Internet Device
5
1423—01/20/09