ICS9LPRS525 Datasheet, PDF (5/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Absolute Maximum Ratings - DC Parameters
PARAMETER
SYMBOL
Maximum Supply Voltage
VDDxxx
Maximum Supply Voltage
VDDxxx_IO
Maximum Input Voltage
V_IH
Minimum Input Voltage
V_IL
Storage Temperature
Ts
Input ESD protection
ESD prot
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied, nor guaranteed.}
3 _{Maximum input voltage is not to exceed VDD}
CONDITIONS
Supply Voltage
Low-Voltage Differential I/O Supply
3.3V Inputs
Any Input
-
Human Body Model
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
Ambient Operating Temp
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Low Threshold Input- High Voltage
Low Threshold Input- FSC = '1' Voltage
Low Threshold Input- FSA,FSB = '1'
Voltage
Low Threshold Input-Low Voltage
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
SYMBOL
Tambient
VDDxxx
VDDxxx_IO
V_IHSE
V_ILSE
V_{IH_FS_TEST}
V_{IH_FS_FSC}
V_{IH_FS_FSAB}
V_{IL_FS}
V_{IL_CFGHI}
V_{IL_CFGMID}
V_{IL_CFGLO}
I_IN
I_INRES
V_OHSE
V_OLSE
I_DDOP3.3
I_DDOPIO
I_DDiAMT3.3
I_DDiAMTIO
I_DDPD3.3
I_DDPDIO
F_i
L_pin
C_IN
C_OUT
C_INX
CONDITIONS
-
Supply Voltage
Low-Voltage Differential I/O Supply
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
V_IN = V_{DD ,} V_IN = GND
Inputs with pull up or pull down resistors
V_IN = V_{DD ,} V_IN = GND
Single-ended outputs, I_OH = -1mA
Single-ended outputs, I_OL = 1 mA
Full Active, C_L = Full load; Idd 3.3V
Full Active, C_L = Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
UNITS
V
V
V
V
°_C
V
Notes
7
7
4,5,7
4,7
4,7
6,7
MIN
0
3.135
0.9975
2
V_SS - 0.3
2
0.7
MAX UNITS
70
°C
3.465
V
3.465
V
V_DD + 0.3 V
0.8
V
VDD + 0.3 V
1.5
V
Notes
10
3
3
8
8
0.7 VDD+0.3 V
V_SS - 0.3 0.35
V
2.4 VDD+0.3 V
1.3
2
V
V_SS - 0.3
0.9
V
-5
5
uA
9, 10
9, 10
9, 10
2
-200
200
uA
2.4
V
1
0.4
V
1
200
mA
70
mA 10
80
mA
10
mA
5
mA
0.1
mA 10
15
MHz
7
nH
1.5
5
pF
6
pF
6
pF
Clk Stabilization
T_STAB
From VDD Power-Up or de-assertion of PD to 1st clock
1.8
ms
Tdrive_CR_off
T_DRCROFF
Output stop after CR deasserted
400
ns
Tdrive_CR_on
Tdrive_CPU
T_DRCRON
T_DRSRC
Output run after CR asserted
CPU output enable after
PCI_STOP# de-assertion
0
us
10
ns
Tfall_SE
Trise_SE
T_FALL
T_RISE
Fall/rise time of all 3.3V control inputs from 20-80%
10
ns
10
ns
SMBus Voltage
V_DD
2.7
5.5
V
Low-level Output Voltage
V_OLSMB
@ I_PULLUP
0.4
V
Current sinking at V_OLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
I_PULLUP
T_RI2C
SMB Data Pin
(Max VIL - 0.15) to
(Min VIH + 0.15)
4
mA
1000
ns
SCLK/SDATA
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
Maximum SMBus Operating Frequency
F_SMBUS
100
kHz
Spread Spectrum Modulation Frequency
f_SSMOD
Triangular Modulation
30
33
kHz
IDT^TM/ICS^TM PC MAIN CLOCK
1484A—04/28/09
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