ICS94211AFLF Datasheet, PDF (5/17 Pages) Integrated Device Technology – Programmable System Frequency Generator for PII/III™

ICS94211
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
PWD
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
Bit2
Bit7 Bit6 Bit5 Bit4
FS3 FS2 FS1 FS0
VCO/REF
Divider
VCO
MHz
CPUCLK PCICLK
MHz
MHz
0 0 0 0 0 447/40 160.01 80.00 40.00
0 0 0 0 1 440/42 150.00 75.00 37.50
0 0 0 1 0 512/44 166.61 83.31 41.65
0 0 0 1 1 392/42 133.64 66.82
33.41
0 0 1 0 0 446/31 206.00 103.00 34.33
0 0 1 0 1 485/31 224.01 112.01 37.34
0 0 1 1 0 513/54 136.02 68.01 34.01
0 0 1 1 1 518/37 200.45 100.23 33.41
0 1 0 0 0 352/21 240.00 120.00 40.00
0 1 0 0 1 514/32 229.99 114.99 38.33
0 1 0 1 0 507/33 219.98 109.99 36.66
0 1 0 1 1 484/33 210.00 105.00 35.00
0 1 1 0 0 352/18 280.00 140.00 35.00
0 1 1 0 1 440/21 300.00 150.00 37.50
0 1 1 1 0 433/25 247.99 124.00 31.00
0 1 1 1 1 483/26 265.99 132.99 33.25
1 0 0 0 0 396/21 270.00 135.00 33.75
1 0 0 0 1 345/19 259.99 129.99 32.50
1 0 0 1 0 440/25 252.00 126.00 31.50
1 0 0 1 1 478/29 236.00 118.00 39.33
1 0 1 0 0 486/30 231.95 115.98 38.66
1 0 1 0 1 491/37 190.01 95.00 31.67
1 0 1 1 0 440/35 180.00 90.00 30.00
1 0 1 1 1 463/39 169.98 85.01 28.34
1 1 0 0 0 371/16 332.00 166.00 41.50
1 1 0 0 1 447/20 320.01 160.01 40.00
1 1 0 1 0 433/20 309.99 154.99 38.75
1 1 0 1 1 310/15 295.91 147.95 36.99
1 1 1 0 0 469/23 291.97 145.98 36.50
1 1 1 0 1 362/18 287.95 143.98 35.99
1 1 1 1 0 476/24 283.98 141.99 35.50
1 1 1 1 1 347/18 276.02 138.01 34.50
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable ± 0.35% Center Spread
0- Running
1- Tristate all outputs
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0441F—08/24/05
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