ICS93V857-XXX Datasheet, PDF (5/11 Pages) Integrated Device Technology – Feedback pins for input to output synchronization

ICS93V8 5 7 - X X X
Timing Requirements
T_A = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency³
freq_op
2.5V+0.2V
33
233
Application Frequency
Range³
freq_App
2.5V+0.2V
60
170
Input clock duty cycle
d_tin
40
60
UNITS
MHz
MHz
%
CLK stabilization
T_STAB
100
µs
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
Low-to high level
propagation delay time
t_PLH1
CLK_IN to any output
High-to low level propagation
delay time
t_PHL1
CLK_IN to any output
Output enable time
Output disable time
Period jitter
Half-period jitter
t_en
t_dis
t_{jit (per)}
t_jit(hper)
PD# to any output
PD# to any output
66/100/125/133/167MHz -40
100 to <170MHz
-100
≥170MHz to 233MHz
-120
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter¹
Phase error
Output to Output Skew
Rise Time, Fall Time
t_sl(I)
1
t_sl(o)
66/100/133/167MHz
1
t_cyc-t_cyc
66/100/125/133/167MHz
t_(phase
4
error)
-50
t_skew
t_r, t_f
Load = 120Ω/16pF
650
TYP
5.5
5.5
5
5
0
40
800
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t_wH/t_c, were
the cycle (t_c) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
MAX UNITS
ns
ns
ns
ns
40
ps
100 ps
50
ps
4
v/ns
2
v/ns
60
ps
50
ps
60
ps
950 ps
0693M—02/19/09
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