ICS87004I-03 Datasheet, PDF (5/12 Pages) Integrated Device Technology – LVCMOS/LVTTL FANOUT BUFFER/DIVIDER Maximum output frequency: 250MHz

ICS87004I-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
TABLE
5B.
AC
CHARACTERISTICS,
V
DD
=
3.3V
±
5%,
V
DDOA
=
V
DDOB
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
250
4.6
40
tsk(pp) Part-to-Part Skew; NOTE 3, 4
tsk(b) Bank Skew; NOTE 3, 5
20
t_R / t_F
Output Rise/Fall Time; NOTE 6
20% to 80%
800
odc
Output Duty Cycle
50
t_EN
Output Enable Time; NOTE 6
5
t_DIS
Output Disable Time; NOTE 6
5
All parameters measured at ƒ ≤ TBDMHz unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDOX/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDOX/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDOX/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
Units
MHz
ns
ps
ps
ps
ps
%
ns
ns
TABLE 5C. AC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDOA = V_DDOB = 1.8V±0.15V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
250
MHz
5.0
ns
40
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
ps
tsk(b) Bank Skew; NOTE 3, 5
20
ps
t_R / t_F
odc
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
20% to 80%
1
ns
50
%
t_EN
Output Enable Time; NOTE 6
5
ns
t_DIS
Output Disable Time; NOTE 6
5
ns
All parameters measured at ƒ ≤ TBDMHz unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDOX/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDOX/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDOX/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
IDT^™ / ICS^™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
5
ICS87004BGI-03 REV. B JUNE 10, 2008