ICS83904-02 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS83904-02
LOW SKEW, 1-TO-4, CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
w/external XTAL
f_MAX
Output Frequency
w/external CLK
12
38.88
200
tp_LH
Propagation Delay, Low-to-High;
NOTE 1
1.4
1.9
2.4
tsk(o) Output Skew; NOTE 2
40
tsk(pp) Part-to-Part Skew; NOTE 2, 3
700
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz – 1MHz
0.16
t_R / t_F
Output Rise/Fall Time
20% to 80%
100
800
odc
Output
Duty Cycle
w/external XTAL
w/external CLK
ƒ< 150MHz
45
46
55
54
t_EN
Output Enable Time; NOTE 5
10
t
Output Disable Time; NOTE 5
10
DIS
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
TABLE
6B.
AC
CHARACTERISTICS,
V
DD
=
3.3V
±
5%,
V
DDO
=
2.5V
±
5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
w/external XTAL
f_MAX
Output Frequency
w/external CLK
12
38.88
200
tp_LH
Propagation Delay, Low-to-High;
NOTE 1
1.5
2.0
2.5
tsk(o) Output Skew; NOTE 2
40
tsk(pp) Part-to-Part Skew; NOTE 2, 3
700
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
0.16
t_R / t_F
Output Rise/Fall Time
20% to 80%
100
800
odc
Output
Duty Cycle
w/external XTAL
w/external CLK
ƒ< 150MHz
45
46
55
54
t_EN
Output Enable Time; NOTE 5
10
t_DIS
Output Disable Time; NOTE 5
10
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
IDT^™ / ICS^™ LVCMOS/LVTTL FANOUT BUFFER
5
ICS83904AG-02 REV. A SEPTEMBER 12, 2007