9FGV0231_16 Datasheet, PDF (5/15 Pages) Integrated Device Technology – 2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR

9FGV0231
2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0231. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
VDDxx
Applies to All VDD pins
Input Voltage
V_IN
Input High Voltage, SMBus V_IHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied nor guaranteed.}
3 _{Not to exceed 2.5V.}
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
V_DD+0.3V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Current Consumption
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Operating Supply Current
I_DDAOP
I_DDOP
VDDA, PLL Mode, All outputs active @100MHz
VDD, All outputs active @100MHz
Suspend Supply Current I_DDSUSP
VDDxxx, PD# = 0, Wake-On-LAN enabled
Powerdown Current
I_DDPD
PD#=0
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Assuming REF is not running in power down state}
7
8
15
18
6
8
0.6
1
UNITS
mA
mA
mA
mA
NOTES
1
1
1
1, 2
Electrical Characteristics–Differential Output Duty Cycle, Jitter, and Skew
Characteristics
TA = T_COM or T_IND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Duty Cycle
t_DC
Measured differentially, PLL Mode
Skew, Output to Output
t_sk3
V_T = 50%
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
45
49.9
55
37
50
12
50
UNITS
%
ps
ps
NOTES
1
1
1,2
IDT® 2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
5
9FGV0231 OCTOBER 18, 2016