9FG830 Datasheet, PDF (5/19 Pages) Integrated Device Technology – Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA
3.3V Logic Supply Voltage VDD
Input Low Voltage
V_IL
Input High Voltage
V_IH
Except for SMBus interface
Input High Voltage
V_IHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied nor guaranteed.}
MIN
GND-0.5
-65
2000
TYP
MAX
4.6
4.6
V_DD+0.5V
5.5V
150
125
UNITS
V
V
V
V
V
°_C
°C
V
NOTES
1,2
1,2
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Parameters
TA = T_COM or T_IND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
T_COM
T_IND
V_IH
V_IL
I_IN
Commmercial range
Industrial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, V_IN = GND, V_IN = VDD
0
-40
2
GND - 0.3
-5
70
°C
1
85
°C
1
V_DD + 0.3 V
1
0.8
V
1
5
uA
1
Input Current
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
V_IN = VDD; Inputs with internal pull-down resistors
200
uA
1
Input Frequency
F_in
SEL14M_25M# = 0
SEL14M_25M# = 1
Pin Inductance
L_pin
Capacitance
C_IN
C_INXTAL
Logic Inputs
Crystal inputs
C_OUT
Output pin capacitance
Clk Stabilization
T_STAB
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
SS Modulation Frequency f_MODIN
Allowable Frequency
(Triangular Modulation)
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_STOP#
t_DRVDS
DIF output enable after
DIF_STOP# de-assertion
Tfall
t_F
Fall time of control inputs
Trise
t_R
Rise time of control inputs
SMBus Input Low Voltage V_ILSMB
SMBus Input High Voltage V_IHSMB
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
SMBus Sink Current
I_PULLUP
@ V_OL
Nominal Bus Voltage
V_DDSMB
3V to 5V +/- 10%
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
SMBus Operating
Frequency
t_FSMB
f_MAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
25
14.31818
7
1.5
5
6
6
2.5
MHz
1
MHz
1
nH
1
pF
1
pF
1
pF
1
ms
1,2
30
33
kHz
1
1
3
cycles 1,3
300
us
1,3
5
ns
1,2
5
ns
1,2
0.8
V
1
2.1
V_DDSMB
V
1
0.4
V
1
4
mA
1
2.7
5.5
V
1
1000
ns
1
300
ns
1
100
kHz
1
IDT^® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
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