9DBL0242 Datasheet, PDF (5/19 Pages) Integrated Device Technology – 2-output 3.3V PCIe Zero-Delay Buffer

9DBL0242 / 9DBL0252 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBL0242 / 9DBL0252. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Input Voltage
V_IN
Input High Voltage, SMBus V_IHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Operation under these conditions is neither implied nor guaranteed.}
3 _{Not to exceed 4.6V.}
MIN
-0.5
-65
2500
TYP
MAX
4.6
V_DD+0.5
3.9
150
125
UNITS NOTES
V
1,2
V
1,3
V
1
°C
1
°C
1
V
1
Electrical Characteristics–Clock Input Parameters
TA = T_AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Crossover Voltage -
DIF_IN
V_CROSS
Cross Over Voltage
150
Input Swing - DIF_IN
V_SWING
Differential value
300
Input Slew Rate - DIF_IN dv/dt
Measured differentially
0.4
Input Leakage Current
I_IN
V_IN = V_{DD ,} V_IN = GND
-5
Input Duty Cycle
d_tin
Measurement from differential wavefrom
45
Input Jitter - Cycle to Cycle J_DIFIn
Differential Measurement
0
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2_{Slew rate measured through +/-75mV window centered around differential zero}
TYP
MAX UNITS NOTES
900
mV
1
mV
1
8
V/ns 1,2
5
uA
55
%
1
125
ps
1
Electrical Characteristics–SMBus Parameters
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
SMBus Input Low Voltage V_ILSMB
V_DDSMB = 3.3V
SMBus Input High Voltage V_IHSMB
V_DDSMB = 3.3V
2.1
SMBus Output Low Voltage V_OLSMB
@ I_PULLUP
SMBus Sink Current
I_PULLUP
@ V_OL
4
Nominal Bus Voltage
V_DDSMB
2.7
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
t_FSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating
Frequency
f_SMB
SMBus operating frequency
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2. _{The device must be powered up for the SMBus to function.}
3. _{The differential input clock must be running for the SMBus to be active}
TYP
MAX
0.8
3.6
0.4
3.6
1000
300
500
UNITS NOTES
V
V
V
mA
V
ns
1
ns
1
kHz 2,3
FEBRUARY 8, 2017
5
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER