8T49NS010 Datasheet, PDF (5/35 Pages) Integrated Device Technology – Ten differential outputs

8T49NS010 DATA SHEET
Table 1. Pin Descriptions¹ (Continued)
Number
Name
Type
46
nCLK_IN
Input
Pullup/
Pulldown
Description
Inverting differential clock input. Internal resistor bias to V_{DD_x}/2.
47
CLK_IN
Input
Pulldown Non-inverting differential clock input.
48
V_{DD_I2C}
Power
Power Supply Voltage for I²C.
49
REF_SEL
Input
Pulldown
Selects between XTAL and CLK. 0 select Xtal (with x2)and 1 selects CLK
input. Refer to Table 4A. LVCMOS interface levels.
50
CAP
51
V_{DD_XTAL}
Power
52
XTAL_IN
Bypass capacitor for internal reference. Should connect cap between this
pin and V_{DD_I2C} pin 48.
Power Supply for crystal.
Crystal oscillator interface, XTAL_IN is the input.
53
XTAL_OUT
Crystal oscillator interface, XTAL_OUT is the output.
54
V_{SS_XTAL}
Power
Power Supply Ground for XTAL circuit. Return for pin 51
55
FB_SEL
Input
Pulldown Feedback Divider select. Refer to Table 4B. LVCMOS interface levels.
56
OUTPUT
TYPE
Input
Pulldown
Selects between FORMAT #1 or FORMAT #2 (with no DC termination)
output levels. “0” selects FORMAT #2 and “1” selects FORMAT #1 type
output structure. Refer to Table 5K. LVCMOS interface levels.
ePad
V_{EE_EP}
Power
Negative supply. Exposed pad must be connected to ground. Return for all
outputs and core supplies Pins 3, 8, 20, 35, 40.
NOTE 1.Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values
Table 2. Input Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLDOWN Input Pulldown Resistor
R_PULLUP
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
Table 3. Output Characteristics
Symbol
Parameter
R_OUT
Output
Impedance
SDATA
Test Conditions
V_{DD_I2C} = 3.3V ± 5%
Minimum
Typical
60
Maximum Units

REVISION 1 11/19/14
5
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER