74FCT38075S Datasheet, PDF (5/11 Pages) Integrated Device Technology – Extremely low RMS Additive Phase Jitter

74FCT38075S DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Start-up Time
t_OR
0.36 to 1.44 V, C_L=5 pF
0.6
t_OF
1.44 to 0.36 V, C_L=5 pF
0.6
t_START-UP Part start-up time for valid
outputs after VDD ramp-up
Propagation Delay
135MHz, Note 1
1.5
3
Buffer Additive Phase Jitter, RMS
125MHz, Integration Range:
12kHz-20MHz
Output to Output Skew
Rising edges at VDD/2, Note 2
50
Device to Device Skew
Rising edges at VDD/2
Max.
200
1.0
1.0
2
4
0.05
65
500
Units
MHz
ns
ns
ms
ns
ps
ps
ps
VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Start-up Time
t_OR
0.5 to 2.0 V, C_L=5 pF
0.6
t_OF
2.0 to 0.5 V, C_L=5 pF
0.6
t_START-UP Part start-up time for valid
outputs after VDD ramp-up
Propagation Delay
135MHz, Note 1
1.8
2.5
Buffer Additive Phase Jitter, RMS
125MHz, Integration Range:
12kHz-20MHz
Output to Output Skew
Rising edges at VDD/2, Note 2
50
Device to Device Skew
Rising edges at VDD/2
Max.
200
1.0
1.0
2
4.5
0.05
65
500
Units
MHz
ns
ns
ms
ns
ps
ps
ps
VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Start-up Time
t_OR
0.66 to 2.64 V, C_L=5 pF
0.6
t_OF
2.64 to 0.66 V, C_L=5 pF
0.6
t_START-UP Part start-up time for valid
outputs after VDD ramp-up
Propagation Delay
135MHz, Note 1
1.5
2.5
Buffer Additive Phase Jitter, RMS
Output to Output Skew
125MHz, Integration Range:
12kHz-20MHz
Rising edges at VDD/2, Note 2
50
Device to Device Skew
Rising edges at VDD/2
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
Max.
200
1.0
1.0
2
4
0.05
65
500
Units
MHz
ns
ns
ms
ns
ps
ps
ps
REVISION A 03/18/15
5
LOW SKEW 1 TO 5 CLOCK BUFFER