6V49205B_16 Datasheet, PDF (5/16 Pages) Integrated Device Technology – Freescale System Clock w/Selectable DDR Frequency

6V49205B DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 6V49205B. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
Maximum Supply Voltage
SYMBOL
VDDxxx
CONDITIONS
Supply Voltage
Maximum Input Voltage
V_IH
Referenced to GND
Minimum Input Voltage
V_IL
Referenced to GND
Storage Temperature
Ts
-
JunctionTemperature
Input ESD protection
Tj
ESD prot
-
Human Body Model
NOTES on Absolute Max Parameters
1 _{Operation under these conditions is neither implied, nor guaranteed.}
MIN
TYP
MAX
UNITS
4.6
V
VDD + 0.5
V
GND - 0.5
V
-65
2000
150
°_C
125
°C
V
Notes
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output DC Parameters
T_AMB = -40 to +85°C; V_DD = 3.3 V +/-5%, All outputs driving test loads (unless noted otherwise).
PARAMETER
SYMBOL
CONDITIONS
Ambient Operating Temp
Supply Voltage
T_AMB
VDDxxx
-
Supply Voltage
Power supply Ramp Time
T_PWRRMP
Power supply ramp must be montonic
Latched Input High Voltage
V_{IH_LI}
Single-ended Latched Inputs
Latched Input Low Voltage
V_{IL_LI}
Single-ended Latched Inputs
Input Leakage Current
I_IN
V_IN = V_{DD ,} V_IN = GND
Operating Supply Current
I_DDOP3.3
All outputs loaded and running
Input Frequency
F_i
MIN
-40
3.135
2.1
V_SS - 0.3
-5
23
TYP
MAX
25
85
3.3
3.465
4
V_DD + 0.3
0.8
5
119
155
25
27
UNITS
°C
V
ms
V
V
uA
mA
MHz
Pin Inductance
L_pin
5
7
nH
Input Capacitance
C_IN
C_OUT
Logic Inputs
Output pin capacitance
1.5
3
5
pF
5
6
pF
Clk Stabilization
C_INX
T_STAB
X1 & X2 pins
From VDD Power-Up or de-assertion of PD
to 1st clock
5
6
pF
3.2
5
ms
Tfall_SE
Trise_SE
T_FALL
T_RISE
Fall/rise time of all 3.3V control inputs from
20-80%
10
ns
10
ns
SMBus Voltage
V_DD
2.7
3.3
V
Low-level Output Voltage
V_OLSMB
@ I_PULLUP
Current sinking at
V_OLSMB = 0.4 V
I_PULLUP
SMB Data Pin
4
SCLK/SDATA
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
0.4
V
mA
1000
ns
SCLK/SDATA
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
SMBus Operating Frequency
F_SMBUS
400
kHz
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 _{Signal is required to be monotonic in this region.}
2 _{Input leakage current does not include inputs with pull-up or pull-down resistors}
3 _{For margining purposes only. Normal operation should have Fin =25MHz}
Notes
2
3
1
1
REVISION R 11/23/16
5
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY