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621S Datasheet, PDF (5/12 Pages) Integrated Device Technology – Low additive phase jitter RMS
621S DATASHEET
AC Electrical Characteristics
VDD=1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Output Frequency
5pF load, Note 4
Output Clock Rise Time
Output Clock Fall Time
Start-up Time
tOR
tOF
tSTART-UP
0.36 to 1.44 V
1.44 to 0.36V
Part start-up time for valid outputs after VDD
ramp-up
Propagation Delay
135 MHz, Note 1
Buffer Additive Phase Jitter, RMS
125MHz, Integration range: 12kHz–20MHz
Output to Output Skew
Rising edges at VDD/2, Note 2
Output Enable Time
Output Disable Time
tEN
CL < 5pF
tDIS
CL < 5pF
VDD=2.5V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Output Frequency
5pF load, Note 4
Output Clock Rise Time
Output Clock Fall Time
Start-up Time
tOR
tOF
tSTART-UP
0.5 to 2.0V
2.0 to 0.5V
Part start-up time for valid outputs after VDD
ramp-up
Propagation Delay
135 MHz, Note 1
Buffer Additive Phase Jitter, RMS
125MHz, Integration range: 12kHz–20MHz
Output to Output Skew
Rising edges at VDD/2, Note 2
Output Enable Time
Output Disable Time
tEN
CL < 5pF
tDIS
CL < 5pF
VDD=3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Output Frequency
5pF load, Note 4
Output Clock Rise Time
Output Clock Fall Time
Start-up Time
tOR
tOF
tSTART-UP
0.66 to 2.64V
2.64 to 0.66V
Part start-up time for valid outputs after VDD
ramp-up
Propagation Delay
135 MHz, Note 1
Buffer Additive Phase Jitter, RMS
125MHz, Integration range: 12kHz–20MHz
Output to Output Skew
Rising edges at VDD/2, Note 2
Output Enable Time
Output Disable Time
tEN
CL < 5pF
tDIS
CL < 5pF
Notes:
1. With rail to rail input clock.
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
4. With external series resistor of 33 positioned close to each output pin.
Min.
1.5
Min.
1.8
Min.
1.5
Typ.
0.6
0.6
Max.
200
1.0
1.0
2
Units
MHz
ns
ns
ms
2
4
ns
0.05 ps
50
65
ps
3 cycles
3 cycles
Typ.
0.6
0.6
Max.
200
1.0
1.0
2
Units
MHz
ns
ns
ms
2.5 4.5
ns
0.05 ps
50
65
ps
3 cycles
3 cycles
Typ.
0.6
0.6
Max.
200
1.0
1.0
2
Units
MHz
ns
ns
ms
2
4
ns
0.05 ps
50
65
ps
3 cycles
3 cycles
REVISION A 03/18/15
5
LOW SKEW 1 TO 4 CLOCK BUFFER