IDT72T3645 Datasheet, PDF (48/57 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
tCLKH
tCLKL
WEN
tENS
tENH
PAF
RCLK
D - (m + 1) words in FIFO
tPAFA
D - m words
in FIFO
tPAFA
D - (m + 1) words
in FIFO
tENS
REN
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NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D=1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT Mode: D=1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS = LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
tCLKH
tCLKL
tENS
tENH
PAE
RCLK
n words in FIFO⁽²⁾,
n + 1 words in FIFO⁽³⁾
tPAEA
n + 1 words in FIFO⁽²⁾,
n + 2 words in FIFO⁽³⁾
tPAEA
tENS
n words in FIFO⁽²⁾,
n + 1 words in FIFO⁽³⁾
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
5907 drw31
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
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