IDT72T3645_09 Datasheet, PDF (46/57 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SCLK
SEN
LD
SI
tSCLK
tSCKH
tSCKL
tSENS
tLDS
tSENH
tLDS
tSDS
BIT 1
EMPTY OFFSET
BIT X⁽¹⁾
BIT 1
FULL OFFSET
tENH
tLDH
tSDH
BIT X⁽¹⁾
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NOTE:
1. X = 10 for the IDT72T3645, X = 11 for the IDT72T3655, X = 12 for the IDT72T3665, X = 13 for the IDT72T3675, X = 14 for the IDT72T3685, X = 15 for the IDT72T3695, X = 16
for the IDT72T36105, X = 17 for the IDT72T36115 and X = 18 for the IDT72T36125.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
LD
WEN
D0 - Dn
tCLK
tCLKH
tCLKL
tLDS
tLDH
tENS
tENH
t DS
t DH
PAE
OFFSET
tLDH
tENH
tDH
PAF
OFFSET
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
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RCLK
LD
tCLKH
tCLK
tCLKL
tLDS
tLDH
tLDS
tLDH
tLDS
tLDH
REN
tENS
tENH
tENS
tENH
tENS
tENH
Q0 - Qn
tA
DATA IN OUTPUT REGISTER
tA
PAE OFFSET VALUE
PAF OFFSET VALUE
tA
PAE OFFSET
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NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
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FEBRUARY 4, 2009