IDT72V3653 Datasheet, PDF (4/30 Pages) Integrated Device Technology – 3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING

IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO^TM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
A0-A35 Port A Data
I/O
AE
Almost-Empty Flag
O
(Port B)
AF
Almost-Full Flag
O
(Port A)
B0-B35 Port B Data
I/O
BE/FWFT Big-Endian/
I
First Word
Fall Through
BM⁽¹⁾
Bus-Match Select
I
(Port B)
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA
Port A Chip
I
Select
CSB
Port B Chip
I
Select
EF/OR
Empty/Output
O
Ready Flag
(Port B)
ENA
Port A Enable
I
ENB
Port B Enable
I
FF/IR
Full/Input
O
Ready Flag
(Port A)
FS0/SD FlagOffsetSelect0/ I
Serial Data,
FS1/SEN FlagOffsetSelect1/ I
Serial Enable
FS2⁽¹⁾
Flag Offset Select 2
I
Description
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
the FIFO is less than or equal to the value in the Almost-Empty B offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
locations in the FIFO is less than or equal to the value in the Almost-Full A offset register, Y.
36-bit bidirectional data port for side B.
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
In this case, depending on the bus size, the most significant byte or word written to Port A is read
from Port B first. A LOW on BE will select Little-Endian operation. In this case, the least significant
byte or word written to Port A is read from Port B first. After Master Reset, this pin selects the timing
mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through
mode. Once the timing mode has been selected, the level on FWFT must be static throughout
device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and
endian arrangement for Port B. The level of BM must be static throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be
asynchronous or coincident to CLKA. EF/OR and AE are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
This is a dual function pin. In the IDT Standard mode, the EF function is selected. EFindicates
whether or not the FIFO memory is empty. In the FWFT mode, the OR function is selected. OR indicates
the presence of valid data on the B0-B35 outputs, available for reading. EF/OR is synchronized to the
LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
This is a dual function pin. In the IDT Standard mode, the FF function is selected. FF indicates
whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory. FF/IR is
synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During
Reset, FS1/SEN and FS0/SD, together with FS2 select the flag offset programming method.
Three offset register programming methods are available: automatically load one of five preset
values (8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on
CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required
to program the offset registers is 22 for the 72V3653, 24 for the 72V3663, and 26 for the 72V3673.
The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
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