IDT71V509 Datasheet, PDF (4/9 Pages) Integrated Device Technology – 128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT

IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
COMMERCIAL TEMPERATURE RANGE
READ OPERATION
Cycle Address
WE CS CEN OE I/O
n
A0
H
L
L
X
X
n+1
X
X
X
X
L
D0
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
Comments
Address and Control meet setup
Contents of Address A0 Read Out
3618 tbl 02
WRITE OPERATION
Cycle Address
WE CS CEN OE I/O
n
A0
L
L
L
X
X
n+1
X
X
X
L
X
D0
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
Comments
Address and Control meet setup
New Data Drives SRAM Inputs
3618 tbl 03
READ OPERATION WITH CLOCK ENABLE USED
Cycle Address
WE CS CEN OE I/O
n
A0
H
L
L
X
X
n+1
X
X
X
H
L
D0
n+2
A2
H
L
L
L
D0
n+3
X
X
X
H
L
D2
n+4
X
X
X
H
L
D2
n+5
A5
H
L
L
L
D2
n+6
A6
H
L
L
L
D5
n+7
A7
?
L
L
L
D6
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
Comments
Address and Control meet setup
Contents of Address A0 Read Out
Contents of Address A0 Read Out
Contents of Address A2 Read Out
Contents of Address A2 Read Out
Contents of Address A2 Read Out
Contents of Address A5 Read Out
Contents of Address A6 Read Out
3618 tbl 04
WRITE OPERATION WITH CLOCK ENABLE USED
Cycle Address
WE CS CEN OE I/O
n
A0
L
L
L
X
X
n+1
X
X
X
H
X
X
n+2
A2
L
L
L
X
D0
n+3
X
X
X
H
X
X
n+4
X
X
X
H
X
X
n+5
A5
L
L
L
X
D2
n+6
A6
L
L
L
X
D5
n+7
A7
?
L
L
X
D6
H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance
Comments
Address and Control meet setup
Clock Ignored at n+1 to n+2 Low-to-High
New Data Drives SRAM Inputs
Clock Ignored at n+3 to n+4 Low-to-High
Clock Ignored at n+4 to n+5 Low-to-High
New Data Drives SRAM Inputs
New Data Drives SRAM Inputs
New Data Drives SRAM Inputs
3618 tbl 05
11.3
4