ICS91305 Datasheet, PDF (4/8 Pages) Integrated Circuit Systems – High Performance Communication Buffer

ICS91305
Switching Characteristics
PARAMETER
Output period
Input period
Duty Cycle¹
SYMBOL
CONDITION
t1
With CL = 30pF
t1
With CL = 30pF
Dt1
Measured at 1.4V; CL = 30pF
MIN
TYP
100.00
(10)
100.00
(10)
40.0
50
Duty Cycle¹
Dt2
Measured at VDD/2 Fout <66.6MHz
45
50
Rise Time¹
tr1
Measured between 0.8V and 2.0V:
CL=30pF
1.2
Fall Time¹
Rise Time¹
tf1
Measured between 2.0V and 0.8V;
CL=30pF
tr1
Measured between 0.8V and 2.0V:
CL=5pF
1.2
1
Fall Time¹
Delay, REF Rising
Edge to CLKOUT
Rising Edge^{1, 2}
tf1
Measured between 2.0V and 0.8V;
CL=5pF
Dr1
Measured at 1.4V
1
0
Output to Output
Skew¹
Tskew
All outputs equally loaded,
CL = 20pF
Device to Device
Skew¹
Tdsk-Tdsk
Measured at VDD/2 on the CLKOUT pins
of devices
0
Cycle to Cycle
Jitter¹
PLL Lock Time¹
Tcyc-Tcyc Measured at 66.66 MHz, loaded outputs
tLOCK
Stable power supply, valid clock presented
on REF pin
Jitter; Absolute
Jitter¹
Tjabs
@ 10,000 cycles
CL = 30pF
-100
70
Jitter; 1 - Sigma¹
Tj1s
@ 10,000 cycles
CL = 30pF
14
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
MAX
7.5
(133)
7.5
(133)
60
55
1.5
1.5
±350
250
700
200
1.0
100
30
UNITS
ns
(MHz)
ns
(MHz)
%
%
ns
ns
ns
ns
ps
ps
ps
ps
ms
ps
ps
0092H—12/02/08
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