IDT723654 Datasheet, PDF (32/37 Pages) Integrated Device Technology – CMOS SyncBiFIFO WITH BUS-MATCHING

IDT723654/723664/723674 CMOS SyncBiFIFO^TM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
ENB
tENS2
tENH
(1)
tSKEW2
1
2
tPAF
AFB [D-(Y2+1)] Words in FIFO2
tPAF
(D-Y2) Words in FIFO2
CLKA
ENA
tENS2
tENH
5608 drw 28
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723654, 4,096 for the IDT723664, 8,192 for the IDT723674.
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.
Figure 26. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
CLKA
CSA
W/RA
MBA
ENA
A0-A35
CLKB
MBF1
CSB
tENS1
tENS1
tENH
tENH
tENS2
tENS2
tDS
W1
tENH
tENH
tDH
tPMF
tPMF
W/RB
MBB
tENS2
tENH
ENB
B0-B35
tEN
tPMR
tMDV
FIFO1 Output Register
tDIS
W1 (Remains valid in Mail1 Register after read)
5608 drw29
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will
have valid data (B9-B35 will be indeterminate).
Figure 27. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
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