ADC1210S Datasheet, PDF (32/37 Pages) NXP Semiconductors – Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

Integrated Device Technology
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Table 24. Output clock register (address 0012h) bit description
Default values are highlighted.
Bit
Symbol
Access Value Description
7 to 4 -
0000 not used
3
DAVINV
R/W
output clock data valid (DAV) polarity
0
normal
1
inverted
2 to 0 DAVPHASE[2:0]
R/W
DAV phase select
000
output clock shifted (ahead) by 6/16  t_clk
001
output clock shifted (ahead) by 5/16  t_clk
010
output clock shifted (ahead) by 4/16  t_clk
011
output clock shifted (ahead) by 3/16  t_clk
100
output clock shifted (ahead) by 2/16  t_clk
101
output clock shifted (ahead) by 1/16  t_clk
110
default value as defined in timing section
111
output clock shifted (delayed) by 1/16  t_clk
Table 25. Offset register (address 0013h) bit description
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 6 -
00
not used
5 to 0 DIG_OFFSET[5:0]
R/W
digital offset adjustment
011111
+31 LSB
...
...
000000
0
...
...
100000
32 LSB
Table 26. Test pattern register 1 (address 0014h) bit description
Default values are highlighted.
Bit
Symbol
Access Value Description
7 to 3 -
00000 not used
2 to 0 TESTPAT_SEL[2:0]
R/W
digital test pattern select
000
off
001
mid scale
010
FS
011
+FS
100
toggle ‘1111..1111’/’0000..0000’
101
custom test pattern
110
‘1010..1010.’
111
‘010..1010’
ADC1210S_SER 3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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