ZSSC3122 Datasheet, PDF (31/64 Pages) List of Unclassifed Manufacturers – Low Voltage Capacitive Sensor Signal Conditioner

ZSSC3122 Datasheet
3.6.1 I²C™ Features and Timing
The ZSSC3122 uses an I²C-compatible communication protocol^†† with support for 100kHz and 400kHz bit rates.
The ZSSC3122 I²C™ slave address (00_HEX to 7F_HEX) is selected by the Device_ID bits in the Cust_Config
EEPROM word (see Table 5.5 for bit assignments). The device will respond only to this address if the
communication lock is set by programming 011_BIN in the Comm_lock bits in the ZMDI_Config EEPROM word (see
Table 5.2 for bit assignments); otherwise, the device will respond to all I²C™ addresses. The factory setting for
the I²C™ slave address is 28_HEX with Comm_lock set. See Figure 3.8 for the I²C™ timing diagram and Table 3.9
for definitions of the parameters shown in the diagram.
Figure 3.8 I²C™ Timing Diagram
SDA
SCL
t_LOW
t_SUDAT
t_HDSTA
t_BUS
t_HDSTA
t_HDDAT
t_HIGH
t_SUSTA
t_SUSTO
Table 3.9 I²C™ Parameters
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS
SCL clock frequency 1⁾
Start condition hold time relative to SCL edge
Minimum SCL clock low width 2⁾
Minimum SCL clock high width 2⁾
Start condition setup time relative to SCL edge
Data hold time on SDA relative to SCL edge
Data setup time on SDA relative to SCL edge
Stop condition setup time on SCL
Bus free time between stop condition and start condition
fSCL
20
tHDSTA
0.1
tLOW
0.6
tHIGH
0.6
tSUSTA
0.1
tHDDAT
0
tSUDAT
0.1
tSUSTO
0.1
tBUS
1
400
kHz
µs
µs
µs
µs
0.5
µs
µs
µs
µs
1 The minimum frequency of 20kHz applies to calibration/test only (required to meet Command Window timing). There is no minimum for NOM.
2 Combined low and high widths must equal or exceed minimum SCL period.
†† _{For details, refer to http://www.standardics.nxp.com/literature/books/i2c/pdf/i2c.bus.specification.pdf or other websites for this specification.}
© 2016 Integrated Device Technology, Inc.
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January 25, 2016