8V97051_17 Datasheet, PDF (31/55 Pages) Integrated Device Technology – Low Power Wideband Fractional RF Synthesizer / PLL

Register 7
Table 12A. Register 7 Bit Allocation^{1 2}
8V97051 Datasheet
REV_ID
(RO)
DEV_ID (RO)
EXT_PHASE EXT_MOD EXT_FRAC
CONTROL
BITS
NOTE 1. SB Bits are Sticky Bits and need to be cleared.
NOTE 2. RO Bits are Read Only Bits.
Table 12B. Register 7: 1-Bit Loss of Digital Lock. Function Description¹
Name
Description
Function
Loss_Dig_Lock LOSS_DIG_LOCK
0 = Locked since last time register was cleared
1 = Loss of Digital Lock since last time register was cleared
NOTE 1. This bit is a sticky bit and needs to be cleared with a SPI write of 1 to detect further Loss of Digital Lock occurrences.
Table 12C. Register 7: 1-Bit Loss of Analog Lock. Function Description¹
Name
Description
Function
0 = Band Selection remained the same since last time register was cleared
Loss_Anlg_Lock LOSS_ANLG_LOCK
1 = Band selection occurred since last time register was cleared
NOTE 1. This bit is a sticky bit and needs to be cleared with a SPI write of 1 to detect further Band Selection occurrences.
Table 12D. Register 7: 1-Bit SPI Error. Function Description¹
Name
Description
Function
Spi_error
SPI_ERROR
0 = No SPI write error detection
1 = SPI Write error
NOTE 1. Spi_error Bit goes high if the SPI interface detects a cycle with the incorrect number of SCLK cycles between nCS asserted Low
and nCS asserted High. The SPI interface expects 32 clock cycles between nCS asserted Low and nCS asserted High. Any
Read/Write via the SPI interface with more or less than 32 clock cycles will result in the Spi_error Bit switched to 1. This bit is a sticky
bit and needs to be cleared with a SPI write of 1 in order to detect further possible SPI Write/Read errors.
©2017 Integrated Device Technology, Inc.
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February 10, 2017