8T49N028 Datasheet, PDF (31/36 Pages) Integrated Device Technology – Fourth Generation FemtoClock NG PLL technology

3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 9.
V_CCO
8T49N028 DATA SHEET
Q1
V_OUT
RL
50Ω
V_CCO - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage
of V_CCO – 2V.
• For logic high, V_OUT = V_{OH_MAX} = V_{CCO_MAX} – 0.75V
(V_{CCO_MAX} – V_{OH_MAX}) = 0.75V
• For logic low, V_OUT = V_{OL_MAX} = V_{CCO_MAX} – 1.6V
(V_{CCO_MAX} – V_{OL_MAX}) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V_{OH_MAX} – (V_{CCO_MAX} – 2V))/R_L] * (V_{CCO_MAX} – V_{OH_MAX}) = [(2V – (V_{CCO_MAX} – V_{OH_MAX}))/R_L] * (V_{CCO_MAX} – V_{OH_MAX}) =
[(2V – 0.75V)/50] * 0.75V = 18.75mW
Pd_L = [(V_{OL_MAX} – (V_{CCO_MAX} – 2V))/R_L] * (V_{CCO_MAX} – V_{OL_MAX}) = [(2V – (V_{CCO_MAX} – V_{OL_MAX}))/R_L] * (V_{CCO_MAX} – V_{OL_MAX}) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW
REVISION 1 10/16/14
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FEMTOCLOCK^® NG CRYSTAL-TO-3.3V, 2.5V MULTIPLE FREQUENCY
CLOCK GENERATOR W/FANOUT BUFFER