79RC32435 Datasheet, PDF (31/53 Pages) Integrated Device Technology – IDTTM InterpriseTM Integrated Communications Processor

IDT 79RC32435
Signal
Symbol
Reference
Edge
266MHz
Min Max
300MHz
Min Max
350MHz
Min Max
400MHz
Min Max
Unit
SPI¹
SCK
SDI
SDO
SCK, SDI,
SDO
Tper_15a
None
100 166667 100 166667 100 166667 100 166667 ns
Thigh_15a,
Tlow_15a
40 83353 40 83353 40 83353 40 83353 ns
Tsu_15b SCK rising or 60
—
60
—
60
—
60
—
ns
Thld_15b
falling
60
—
60
—
60
—
60
—
ns
Tdo_15c SCK rising or 0
60
0
60
0
60
0
60
ns
falling
Tpw_15e
None
2(ICLK) — 2(ICLK) — 2(ICLK) — 2(ICLK) —
ns
Table 13 SPI AC Timing Characteristics
1. _{In SPI mode, the SCK period and sampling edge are programmable. In PCI mode, the SCK period is fixed and the sampling edge is rising.}
Condi-
tions
Timing
Diagram
Reference
SPI See Figures
SPI ^{16, 17, and 18.}
SPI See Figures
SPI ^{16, 17, and 18.}
SPI
Bit I/O
Tper_15a
SCK
SDI
MSB bit 6
SDO
MSB
bit 6
Thigh_15a
Tlow_15a
Tsu_15b
bit 5
bit 4
bit 3
Tdo_15c
bit 5
bit 4
bit 3
Thld_15b
bit 2
bit 1
LSB
bit 2
bit 1
LSB
Control bits CPOL = 0, CPHA = 0 in the SPI Control Register, SPC.
Figure 16 SPI AC Timing Waveform — Clock Polarity 0, Clock Phase 0
Tper_15a
SCK
SDI
SDO
Thigh_15a
Tlow_15a
Tsu_15b
Thld_15b
MSB bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
LSB
Tdo_15c
MSB bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
Control bits CPOL = 0, CPHA = 1 in the SPI Control Register, SPC.
Figure 17 SPI AC Timing Waveform — Clock Polarity 0, Clock Phase 1
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January 19, 2006