5P49V6901 Datasheet, PDF (30/37 Pages) Integrated Device Technology – Programmable Clock Generator

5P49V6901 DATASHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs generate ECL/LVPECL compatible
outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality.
These outputs are designed to drive 50 transmission lines.
Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. The figure
below show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist and
it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
LVPECL
Zo=50ohm
Zo=50ohm
R1
50ohm
3.3V
+
-
R2
50ohm
Input
RTT
50ohm
3.3V LVPECL Output Termination (1)
3.3V
LVPECL
R3
125ohm
Zo=50ohm
3.3V
Zo=50ohm
R1
84ohm
R4
125ohm
3.3V
+
-
R2
84ohm
Input
3.3V LVPECL Output Termination (2)
PROGRAMMABLE CLOCK GENERATOR
30
NOVEMBER 11, 2016