IDT74FCT833A Datasheet, PDF (3/8 Pages) Integrated Device Technology – FAST CMOS PARITY BUS TRANSCEIVER

IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE⁽²⁾
Inputs
OET OER CLR CLK
L
H
H
↑
L
H
H
↑
L
H
H
↑
L
H
H
↑
H
L
H
↑
H
L
H
↑
H
L
H
↑
H
L
H
↑
——
L
—
RI (∑ or H’s)
H (Odd)
H (Even)
L (Odd)
L (Even)
NA
NA
NA
NA
—
H
H
H H or L
—
H
H
L
—
—
H
H
H
↑
H or L (Odd)
H
H
H
↑
H or L (Even)
L
L
H
↑
L
L
H
↑
L
L
H
↑
L
L
H
↑
H (Odd)
H (Even)
L (Odd)
L (Even)
NOTES:
1. Output state assumes HIGH output pre-state.
2. H = HIGH
L = LOW
↑ = LOW-to-HIGH transition of clock
*No change to stored Error State
Z=
NA =
–=
TI Incl Parity
(∑ of H’s)
RI
NA
NA
NA
NA
NA
NA
NA
NA
H (Odd)
H
H (Even)
H
L (Odd)
L
L (Even)
L
—
NA
—
Z
—
Z
—
Z
—
Z
NA
NA
NA
NA
NA
NA
NA
NA
High Impedance
Not Applicable
Don’t Care or Irrelevant
Outputs
TI Parity ERR⁽¹⁾ Function
H
L
H
H
L
L
L
H
H
Transmit data from R Port
L
to T Port with parity;
H
receiving path is disabled.
L
NA NA
NA NA
NA NA
NA NA
H
Receive data from T Port
L
to R Port with parity test
H
resulting in flag:
L
transmitting path is disabled.
NA NA
H
Clear the state of error flag
register.
Z
Z
Z
Z
Z
Z
Z
Z
*
Both transmitting and
H
receiving paths are disabled.
H
Parity logic defaults to
L
transmit mode.
H
H
H
L
L
H
L
L
L
Forced-error checking.
H
L
H
2557 tbl 03
Odd =
Even =
I=
Odd number of logic one’s
Even number of logic one’s
0, 1, 2, 3, 4, 5, 6, 7
7.21
3