IDT70T653M Datasheet, PDF (3/24 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Pin Configuration^(1,2,3)
Preliminary
Industrial and Commercial Temperature Ranges
70T653M BC
BC-256^(4,5)
10/07/03
256-Pin BGA
Top View
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 A11 A12
A13 A14 A15 A16
NC TDI NC A17L A14L A11L A8L BE2L CE1L OEL INTL A5L A2L A0L NC NC
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14 B15
B16
I/O18L NC TDO A18L A15L A12L A9L BE3L CE0L R/WL NC A4L A1L NC I/O17L NC
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10 C11 C12 C13 C14 C15 C16
I/O18R I/O19L VSS A16L A13L A10L A7L BE1L BE0L SEML BUSYL A6L A3L _{OPTL I/O17R} I/O16L
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15 D16
I/O20R I/O19R I/O20L VDD VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10 E11
E12 E13
E14 E15 E16
I/O21R I/O21L I/O22L VDDQL VDD VDD VSS VSS VSS VSS VDD VDD VDDQR I/O13L I/O14L I/O14R
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
I/O23L I/O22R I/O23R VDDQL VDD NC VSS VSS VSS VSS VSS VDD VDDQR I/O12R I/O13R I/O12L
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10 G11 G12 G13 G14 G15 G16
I/O24R I/O24L I/O25L VDDQR VSS VSS _VSS VSS VSS _{VSS VSS VSS VDDQL} I/O10L I/O11L I/O11R
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15 H16
I/O26L I/O25R I/O26R VDDQR VSS VSS ^{VSS VSS VSS VSS VSS VSS VDDQL} I/O9R IO9L ^I/O10R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10 J11
J12
J13
J14
J15
J16
I/O27L I/O28R I/O27R VDDQL ZZR VSS VSS VSS VSS _{VSS VSS ZZL VDDQR I/O8R I/O7R I/O8L}
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15 K16
I/O29R I/O29L I/O28L VDDQL VSS ^VSS VSS ^VSS VSS ^VSS VSS ^VSS VDDQR I/O6R I/O6L I/O7L
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13 L14
L15 L16
I/O30L I/O31R I/O30R VDDQR VDD NC VSS VSS VSS VSS VSS VDD VDDQL I/O5L I/O4R I/O5R
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10 M11 M12 M13 _{M14 M15} M16
I/O32R I/O32L I/O31L VDDQR VDD VDD VSS VSS VSS VSS VDD VDD VDDQL I/O3R I/O3L I/O4L
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10 N11 N12 N13 N14 N15 N16
I/O33L I/O34R I/O33R VDD VDDQR VDDQR VDDQL ^VDDQL VDDQR VDDQR VDDQL ^VDDQL VDD I/O2L I/O1R I/O2R
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11 P12 P13 P14 P15 P16
I/O35R I/O34L TMS A16R A13R A10R A7R BE1R BE0R SEMR BUSYR A6R A3R I/O0L I/O0R I/O1L
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 R15 R16
I/O35L NC TRST A18R A15R A12R A9R BE3R CE0R R/WR VSS A4R A1R OPTR NC NC
,
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11
T12
T13
T14
T15
T16
NC TCK NC A17R A14R A11R A8R BE2R CE1R OER INTR A5R A2R A0R NC NC
5679 drw 02f
NOTES:
,
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
3